1. Field of the Invention
The invention is in the field of integrated circuits, and solves a problem related to reliability of integrated circuits having metal programmable logic.
2. Description of the Prior Art
Integrated circuits (xe2x80x9cICsxe2x80x9d) typically have a substrate, an active region on the substrate containing a large plurality of circuit elements such a transistors, resistors, capacitors etc., and a region adjacent the active region which has a plurality of conductor layers and insulating layers interspersed between the conductor layers. The conductor layers each include a large number of conductor tracks which are used to provide power to the circuit elements, as well as for signal routing between the elements.
During design and testing of an integrated circuit, or even after an IC has been in production, it is often necessary or desirable to revise the circuit operation to remove faults or to otherwise improve circuit operation. At the most severe end of the spectrum of revisions, the changes may require modifications to the masks which define the content and arrangement of circuit elements on the substrate. More frequently, however, the designer has anticipated potential problems and has included sufficient circuit elements on the integrated circuit to fix the problem. For example, the designers may include a selection of buffer circuit elements to remove timing problems in the signal routing. It is then a matter of modifying the conductor routing so as to decouple and/or couple certain of the circuit elements so as to implement the fix.
Additionally, many chip designs incorporate an identification (xe2x80x9cIDxe2x80x9d) module which is readable by software. The purpose of the module ID is to allow software to identify the hardware and, based on the ID, configure the chip and the corresponding software. As the industry moves to systems on a chip design, where proven circuit modules are xe2x80x9cplugged intoxe2x80x9d the IC, it will be desirable for each circuit module to have a corresponding module ID.
When making a circuit fix/enhancement to a particular module, it will typically be desirable to change the output of the module ID circuit, so that software will read a different ID code reflecting the change. One way to implement a module ID is with metal programmable logic. Metal programmable logic includes a region on an IC in which a plurality of logic gates are formed. The logic function implemented by these gates is selected by controlling how the gates are interconnected with conductors in the conductors layers. Changing the module ID is but one of many uses for metal programmable logic.
Integrated circuits typically contain built-in circuitry which allows the integrated circuit to be thoroughly tested. One well-known technique is boundary scan testing in which a chain of registers and flip-flops are included on the IC. Boundary scan circuits allow digital inputs to be applied to individual circuits while allowing monitoring of the output of a circuit in response to the known input. When the output is not as expected, the circuit then has a fault.
A problem with metal selectable logic that was recognized by the present inventors is that xe2x80x9cdeselectedxe2x80x9d transistors, i.e. transistors of a logic cell provided on the IC substrate but which are decoupled from the logic path of the cell by removing conductors which would otherwise couple these transistors to other transistors in the logic path, are not scan testable with typical scan test circuits. This is because scan test circuits are commonly coupled to the input and output of a cell. Thus, if the logic configuration is changed for example by coupling the output to a different node in the cell, thereby removing one or more transistors from the logic path between the cell input and the cell output, scan test data input to the cell input and read from the cell output will no longer be influenced by deselected transistors. If one of these deselected transistors has a fault, it will not be observed by the scan test. However, deselected transistors usually form a gate coupled between power supply rails of the logic cell. A failure mode is for deselected transistors to form an unwanted current path between the power supply rails which causes hot spots that can lead to premature failure of neighboring gates and malfunctioning of the integrated circuit. This normally occurs with xe2x80x9cstuck onxe2x80x9d faults in which a transistor is stuck in a conductive state.
Accordingly, it would be desirable to provide an IC with metal programmable logic in which the potential for damage to selected gates from non-selected gates is substantially reduced.
Generally, metal programmable logic cells are switchable between two or more logic configurations. Consequently, it would be possible to provide extra circuitry in the scan test circuit to test deselected gates. However, this is not desirable as it would add complexity, consume additional die area, and generally increase the cost of the integrated circuit.
Accordingly, it would be desirable to increase the confidence in the integrity of integrated circuits having metal programmable logic cells with deselected transistors without providing additional circuitry to actually scan test deselected gates.
Generally speaking, the invention is a method of improving the reliability of an integrated circuit having a metal-programmable logic cell in which the logic cell can be selected during manufacturing to have one of a first logic configuration and a second logic configuration by selection of conductor routing paths to select and deselect transistors for inclusion in a logic path of the cell. At least one transistor is deselected from the logic path of the cell by placing conductor routings so that the at least one transistor is functionally decoupled from the logic path of the cell. The deselected transistor is also decoupled from power supply rails of the cell so that no conductive path extends through the deselected transistor between the cell power supply rails.
When changing from one logic configuration to another, instead of merely changing conductor routing so as to deselect one or more transistors as in known methods, the present method goes further and makes additional conductor routing changes to provide an open circuit in the path of the main current channel of the deselected transistors. In this way, if a deselected transistor were to have a xe2x80x9cstuck onxe2x80x9d fault in which it remained conductive despite its control terminal being decoupled from other, selected transistors in the logic path, there will be no conductive path through the deselected transistor(s) between the cell power supply rails. In this way, hot spots and the reliability problems to the integrated circuit which this entails are avoided.
The method does not alter the fact that in the completed integrated circuit with a typical scan test circuit the deselected transistor(s) are not scan testable. Rather, the method removes a major source of reliability problems posed by xe2x80x9cstuck onxe2x80x9d fault conditions. Thus, the method provides an integrated circuit with deselected transistors with enhanced reliability. This alleviates the need to provide additional, area consuming elements in the scan test circuitry to test for xe2x80x9cstuck onxe2x80x9d faults, since even if a deselected transistor were to have such a fault, the reliability problem posed by this fault in prior art circuits has been removed by the method according to this invention.
The invention also relates to an integrated circuit manufactured according to the above method in which deselected transistors in a metal programmable logic cell have conductor routings with an open circuit so that no current path extends through the deselected transistors between the supply rails.
According to another aspect of the invention, an integrated circuit has an ID module comprising a metal programmable logic cell with deselected transistors electrically decoupled from the supply rails.
These and other objects, features and advantages of the invention will become apparent from the following detailed description and the drawings, both of which are illustrative and not limiting.